FPGA IP Design Verification Engineer

Job Details

Job Description:

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.

Join us in our journey to becoming the #1 FPGA company!

We have put together a best-in-class team that delivers FPGA IPs that will be consumed by standard as well as industry-leading solutions. As a Senior Digital Design Verification Engineer at Altera, you'll verify the design and implementation of our cutting edge AXI protocol IPs and RISC-V CPU.

Role

• Verification of the digital design, golden models and micro-architecture of the AXI protocol IPs and RISC-V CPU using advanced verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
• Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
  
  

Qualifications

Minimum Qualifications:

• Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
• At least 5 years of validated experience.
• Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.
• Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.
• Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
  
  

Preferred Qualifications

• Expertise in standard bus protocols (e.g. AXI4, AXI5, RISC-V CPU, External Memory) a huge plus.
• Experience in verifying complex AXI Interconnect, AXI BFM development , RISC-V CPU verification.
• Perl, Python, C/C++ programming language experience.
• Good debugging and analytical skills.
• Good interpersonal skills & dream to work as a phenomenal teammate.
  
  

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Ecospace 1

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.