SoC Logic Design Engineer

Job Details

Job Description:

• As a key member of Full Chip Integration Reliability Team you will be responsible for all aspects of FPGA power intent and reliability.
• Responsibilities include power intent verification using UPF, power electrical rule checking, power up and power down spice simulation at block level and system level power delivery analysis along with silicon correlation, EM and IR closure, aging, and die package bump and ball planning.
• Good cross functional collaboration needed to verify, debug, and signoff system level reliability items.
  
  

Qualifications

• BS/MS in Electrical Engineering
• Circuit design experience for minimum of 5 years
• Familiar with Spice or Power Integrity analysis for minimum of 3 years
• Experience with UPF, Verdi, Redhawk, power IR/EM, physical design, and power on sequence is a plus
• Comfortable with PERL/Python, TCL, Linux Shells
• Excellent execution and strong drive to close complex design issues
• Good communication and presentation skills to enable cross functional interaction
  
  

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Ecospace 1

Additional Locations:

Penang 15

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.