Altera - IP Design Lead

Job Details

Job Description:

Job Description

Become a member of one of the largest engineering companies in the world!

Altera’s Custom IP Solutions Engineering (IPSE) team develops comprehensive IP solutions to provide customers easy and efficient access to the capabilities of Altera's FPGA devices. These solutions are provided as highly configurable intellectual property (IP) cores that are fully integrated with Altera’s software CAD tool, Quartus Prime. The IP and Solutions engineering team is responsible for delivering Networking and SmartNIC IP and solutions as part of the Platform Solutions Group.

The PSG IP and Solutions Engineering team is seeking an experienced IP Design Lead to help define and lead the next generation Transceiver solutions for PCIe, Ethernet, SmartNIC, Networking and Communications segments for programmable logic products. This forward-looking dynamic role provides unique opportunities to influence future product direction requiring a strong technical leader with strong leadership, personal communication and collaboration skills.

• The successful candidate will bring design solutions experience for Data Center, and/or Communications, Networking, and/or Wireless domains, ideally covering both hardware and software, with knowledge of FPGA architecture, transceiver architecture and higher level protocols.
• Ideally the candidate will have experience leading large design teams on strategic projects implementing designs for FPGA in networking and storage would be a distinct advantage.
• You will lead a complex global IP Solutions program driving various aspects of the functions including RTL design, timing closure, hardware validation etc.
• You will work with cross-functional teams including planning, architecture, silicon design, software and platforms to define and drive delivery of holistic customer solutions that meet market requirements and capabilities comprising silicon, soft IP, applications, SW and tools support.
• Manage overall program including planning, tracking, execution, executive reporting apart from getting involved hands-on in project execution.
• Align with global stakeholders in various sites, anticipate and mitigate risks.
  
  

Qualifications

13+ years of experience with a MS degree in IP design of complex networking, Ethernet & PCIe based IPs and subsystems. Good understanding of FPGA IP design and implementation methodology.

• Must have microarchitecture knowledge of PCIe, Ethernet or transceivers.
• In depth knowledge with Verilog, System Verilog, RTL design, FPGA design, and FPGA design tools.
• In depth knowledge with one of high speed serial protocols: PCIe/Ethernet.
• Experience in Design and verification tools: simulation tools and debug tools.
• End-to-end System level knowledge including design, software, firmware and hardware.
• Proactive, self-motivated and quick learner.
• Good team spirit and ability to deliver to schedule.
• Excellent analytical and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to multi-task and work in a dynamic environment.
• Must have experience working closely with customers, understanding their systems and providing optimized solutions.
• Good communication and presentation skills a must.
• Should have ability to work in multi site execution and ability to influence across groups
• Strong experience in networking standards and protocol.
• Good to have programming skills (C, C++, perl, python, tcl, etc.).
  
  

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Ecospace 1

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.