FPGA Silicon Design Verification Engineer
Altera
Tanggal: 2 minggu yang lalu
Kota: Lembang, West Java
Jenis kontrak: Penuh waktu
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Job Details
Job Description:
Regular
Shift
Shift 1 (India)
Primary Location:
Ecospace 1
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Job Description:
- Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
- Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
- Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
- Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.
- Run IO PHY tests with AMS (Digital/Analog Mixed Signal Simulation).
- Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
- BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.
- Related technical experience should be in/with: Pre Silicon Validation/Verification.
- JESD 79-5 DDR5, JESD209-5 LPDDR5, JESD 209-4 LPDDR4, DDR PHY Interface (DFI 5.1)
- Tessent SSN scan
- OVM/UVM, System Verilog, constrained random verification methodologies.
Regular
Shift
Shift 1 (India)
Primary Location:
Ecospace 1
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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